The accompanying FIG. 2 shows a lateral cross-sectional view of a trench transistor device 10, which is configured as a DMOS transistor and has two MOS trench transistor cells in the example illustrated. A MOS transistor device of this type is the subject matter of DE 102 07 309 A1 from Infineon Technologies AG. The MOS transistor device illustrated is formed in a semiconductor region 20, in a substrate region 21 and an epitaxial region 22 of the first conductivity type, which may be the n type by way of example, and has alternately in each case a mesa region M having the width DMesa adjoining a deep gate trench 30 having the width DTrench. A multiplicity of MOS transistor cells of this type may be formed in the lateral direction that proceeds toward the right and left and is indicated by the double arrow X in FIG. 2. The wall regions of the gate trenches 30 are lined with a gate oxide GOX, for example made of silicon oxide, that serves as an insulation region. The gate oxide GOX has a maximum thickness DGOX in a lower region 30u of the gate trench 30. The gate oxide GOX is very much narrower in the upper region 30o of the gate trench 30. A gate electrode G projects into the deep trench 30 in a manner encapsulated in insulating fashion by the gate oxide GOX, said gate electrode being insulated toward the outside by the gate oxide GOX. By virtue of the aforementioned thinning of the gate oxide GOX toward the upper region 30o of the gate trench 30, the gate electrode G has a so-called field plate structure in such a way that the gate oxide GOX is thickened from the upper region 30o of the gate trench 30 via a field plate step FPS to the lower section 30o of the gate trench 30. In the topmost section of the mesa region (M) a source electrode region (S) is formed with a doping corresponding to the first conductivity type (in this case n+ by way of example). A body region B of a second conductivity type (for example p) lies directly below the source electrode S. A body reinforcement BV is situated at the location of the body contact.
FIG. 2 makes it clear that the bottom of the body reinforcement BV, that is to say the lower boundary thereof, is situated above the field plate step FPS, that is to say that the depth of the body reinforcement BV measured in the direction of the arrow T is less than the depth tFPS of the field plate step FPS likewise specified in the direction of the arrow T.
A drain electrode D lying opposite the deep trench 30 is situated in the substrate region 21 highly doped with the first conductivity type. Small local zones A1, A2, A3 indicated in hatched fashion specify the probable locations of the avalanche breakdown, which normally lie at the locations A1 in the base region 30b of the gate trench 30 but in the high-current case abruptly move upward to the locations specified by A2 and A3. That is to say that if the current density in the avalanche case reaches high values at which the background doping of the epitaxial layer 22 in the mesa M is appreciably influenced, the electric field distribution changes in such a way that the breakdown location in the mesa M jumps upward either to the locations A2 beside the field plate step FPS or to the location A3 at the bottom of the body reinforcement BV or to the body B itself if no body reinforcement BV is present. The jump of the breakdown location to the field plate step FPS (locations A2) is disadvantageous for a number of reasons: situated directly in the region of the field plate step FPS is the gate oxide GOX, which can be damaged by the hot charge carriers that arise during the avalanche or be adversely influenced in terms of the electrical effect by incorporation of charge carriers. Furthermore, this breakdown location A2 is homogeneously distributed along the gate trench 30, so that charge carriers can also arise at the level of the source zone S and thus form a highly unfavorable current path toward the body contact. As a consequence thereof, a parasitic bipolar transistor situated below the source electrode may trigger and destroy the component. In principle, the static breakdown voltage at the location A2 of the field plate step is also lowered by approximately 25% of the nominal component breakdown voltage relative to the breakdown location A1 at the trench bottom, which may in turn lead to an unfavorable breakdown behavior.
This jumping-up of the breakdown location in the high-current case will be explained below with reference to FIGS. 5A, B, C and D, which graphically illustrate simulation results for the avalanche case. It should be noted that FIGS. 5A-D, on account of the mirror symmetry in the lateral direction X, in each case show the electric field distribution (through field lines) only for half the mesa width ½ DMesa and half the trench width ½ DTrench. During the simulation, the current density was increased from left to right, i.e., from FIG. 5A to FIG. 5D, FIG. 5D illustrating the high-current case. It can clearly be seen that, in the avalanche cases A, B, C the location A1 of the probable breakdown lies in the bottom region of the gate trench, while the high-current case of FIG. 5D exhibits two further locations A2 and A3 having increased field strength which indicate a probable breakdown location. The location A2 lies beside the field plate step FPS and the location A3 lies at the bottom of the customary body reinforcement BV (cf. FIG. 2).
In planar transistor concepts, in order to achieve good avalanche strength, additional body reinforcement implantations have hitherto been added directly below the body contacts in order, on the one hand, to fix the avalanche breakdown location there and, on the other hand, to be able to optimally extract the charge carriers generated. In trench transistor concepts such as in the case of the concept described in the introduction, either a trench contact with a body reinforcement zone or directly one or a plurality of body reinforcement zones have been introduced in the cell center between two gate trenches in order likewise to fix the breakdown location there and to be able to optimally extract the charge carriers generated. These solutions function very well with regard to the avalanche strength but require a great deal of space in order not to influence the channel region and thus increase the threshold voltage by virtue of the body reinforcement.